VDAT 2026

Call for paper

Important Dates

Paper Submission

Deadline:April 30, 2026

Acceptance Notification

Date:June 30, 2026

Early Bird Registration

Deadline: July 6, 2026

Camera-ready Submission

Deadline: July 31, 2026

VDAT 2026 Conference

The VDAT 2026 conference provides a platform for researchers and practitioners to explore how VLSI and Embedded Systems can drive disruptive advancements for the next generation.

Paper Submission

Submit full-length papers (6 pages max) with 200-word abstracts. Blind review format required - omit author names. Only original, unpublished work accepted. PDF submission with complete contact details.

Paper Format

Camera-ready IEEE two-column format following standard IEEE proceedings specifications for consistency and professional presentation.

Conference Tracks

Track 1 : VLSI & System-on-Chip (SoC) Design

Digital, Analog & Mixed-Signal Design

Low-Power & High-Performance Architectures

Heterogeneous SoC Integration

Embedded & Real-Time Systems

Memory Subsystems & On-Chip Interconnects

Track 2 : Nanoelectronics, Emerging Devices & Beyond-CMOS Technologies

FinFET, GAA, Nanosheet & Advanced Transistor Structures

2D Materials & Novel Semiconductor Devices

Spintronics & Neuromorphic Devices

Device Modeling & Reliability

Cryogenic & Advanced Device Technologies

Track 3 : Electronic Design Automation (EDA), CAD & AI-Driven Design

Physical Design & Place-and-Route

Design Space Exploration

AI/ML for EDA & Automation

Statistical & Formal Verification

Design Automation for Advanced Technology Nodes

Track 4 : Design Automation for Advanced Technology Nodes

Hardware Accelerators for Deep Learning

Edge AI & Low-Power AI Systems

In-Memory & Near-Memory Computing for AI

AI for Semiconductor Manufacturing & Yield

Efficient Architectures for LLMs & Emerging AI Models

Track 5 : Verification, Testing, Reliability & Hardware Security

Design-for-Testability (DFT) & Built-In Self-Test (BIST)

Hardware Trust & Security Architectures

Fault Tolerance & Resilient Systems

Aging, Variability & Radiation Effects

Secure SoC & Cryptographic Hardware

Track 6 : 3D-IC, Advanced Packaging & Heterogeneous Integration

2.5D/3D IC Integration

Chiplets & System-in-Package

Thermal & Power Integrity in 3D Systems

Advanced Interconnect & TSV Technologies

Packaging Solutions for AI & High-Performance Systems

Track 7 : Quantum & Future Computing Architectures

Quantum Computing Devices & Architectures

Quantum Circuit Design & Error Correction

Cryogenic CMOS for Quantum Systems

A Beyond-CMOS Computing Paradigms

Hybrid Classical–Quantum Architectures

Submission Guidelines and Review Process

  • 1
    Submit a single PDF containing all the information listed below.
  • 2
    Paper Format: Papers should be in PDF format following the IEEE Conference paper format.
  • 3
    Page Limit: Submissions must not exceed six A4-sized pages.
  • 4
    Submission Link: Upload your manuscript via the following link: Submit Here.
  • 5
    Review Process: A double-blind review process will be followed, so ensure no author names or identifying information is included in the manuscript.
  • 6
    Abstract: Include an abstract of 250 words with a maximum of five keywords.
  • 7
    Notification: Authors will be notified via email regarding acceptance and required revisions.
  • 8
    Final Submission: Revised camera-ready copies must be submitted within the specified deadline following the final submission guidelines.
  • 9
    Registration Requirement: At least one author must register for the conference to present and publish the paper. Separate registration is required for each paper presented by the same author.